The production of integrated circuits begins with the creation of high-quality semiconductor wafers. During the wafer fabrication process, the wafers may undergo multiple masking, etching, and dielectric and conductor deposition processes. In addition, metallization, which generally refers to the materials, methods and processes of wiring together or interconnecting the component parts of an integrated circuit located on the surface of a wafer, is critical to the operation of a semiconductor device. Typically, the “wiring” of an integrated circuit involves etching trenches and “vias” in a planar dielectric (insulator) layer and filling the trenches and vias with a metal.
In the past, aluminum was used extensively as a metallization material in semiconductor fabrication due to the leakage and adhesion problems experienced with the use of gold, as well as the high contact resistance which copper experienced with silicon. Other metallization materials have included Ni, Ta, Ti, W, Ag, Cu/Al, TaN, TiN, CoWP, NiP and CoP. Over time, the semiconductor industry has slowly been moving to the use of copper for metallization due to the alloying and electromigration problems that are seen with aluminum. When copper is used as the trench and via filling material, typically a barrier layer of another material is first deposited to line the trenches and vias to prevent the migration of copper into the dielectric layer. Barrier metals may be W, Ti, TiN, Ta, TaN, various alloys, and other refractory nitrides, which may be deposited by CVD, PFD, or electrolytic plating. To achieve high quality filling of the trenches and vias, extra metal is often deposited over areas of the wafer above and outside the trenches and vias. After filling, planarization is typically conducted to remove the extra metal down to the dielectric surface. Planarization leaves the trenches and vias filled and results in a flat, polished surface.
Because of the high degree of precision required in the production of integrated circuits, an extremely flat surface is generally needed on at least one side of the semiconductor wafer to optimize the fabrication process, as well as to ensure proper accuracy and performance of the microelectronic structures created on the wafer surface. As the size of the integrated circuits continues to decrease and the density of microstructures on an integrated circuit increases, the need for precise wafer surfaces becomes more important. Therefore, between each processing step, it is usually necessary to polish or planarize the surface of the wafer to obtain the flattest surface possible.
Chemical mechanical planarization (CMP) is a technique conventionally used for planarization of semiconductor wafers. For a discussion of chemical mechanical planarization (CMP) processes and apparatus, see, for example, Arai et al., U.S. Pat. No. 4,805,348, issued February 1989; Arai et al., U.S. Pat. No. 5,099,614, issued March 1992; Karlsrud et al., U.S. Pat. No. 5,329,732, issued July 1994; Karlsrud, U.S. Pat. No. 5,498,196, issued March 1996; and Karlsrud et al., U.S. Pat. No. 5,498,199, issued March 1996.
Typically, a CMP machine includes a wafer carrier configured to hold, rotate, and transport a wafer during the process of polishing or planarizing the wafer. During a planarization operation, a pressure applying element (e.g., a rigid plate, a bladder assembly, or the like) that may be integral to the wafer carrier, applies pressure such that the wafer engages a polishing surface with a desired amount of force. The carrier and the polishing surface are rotated, typically at different rotational velocities, to cause relative lateral motion between the polishing surface and the wafer and to promote uniform planarization.
In general, the polishing surface comprises a horizontal polishing pad that has an exposed abrasive surface of, for example, cerium oxide, aluminum oxide, fumed/precipitated silica or other particulate abrasives. Polishing pads can be formed of various materials, as is known in the art, and are available commercially. Typically, the polishing pad may be blown polyurethane, such as the IC and GS series of polishing pads available from Rodel Products Corporation in Scottsdale, Ariz. The hardness and density of the polishing pad depend on the material that is to be polished. An abrasive slurry may also be applied to the polishing surface. The abrasive slurry acts to chemically weaken the molecular bonds at the wafer surface so that the mechanical action of the polishing pad can remove the undesired material from the wafer surface.
While CMP tends to work very well for planarization if the correct slurry and process parameters are used, it may leave stresses in the worked workpiece, leading to subsequent cracking and shorting between metal layers. In addition, the semiconductor industry is increasingly using low k dielectrics, which tend to be fragile materials. CMP may result in shearing or crushing of these fragile layers. CMP also has a tendency to cause dishing in the center of wide metal features, such as trenches and vias, oxide erosion between metal features, and oxide loss of the dielectric.
Electrochemical planarization is an attractive alternative to CMP because it does not impart significant mechanical stresses to the workpiece and, consequently, does not significantly reduce the integrity of the low k dielectric devices. Further, electrochemical planarization is less likely to cause dishing, oxide erosion and oxide loss of the dielectric layer.
Electrochemical planarization is based on electroetching and electrochemical machining, that is, the removal of a thin layer of metal from a substrate by the combination of an electrochemical solution and electricity. FIG. 1 shows a conventional prior art electroetching cell. A tank 2 holds a liquid electrolyte 4, such as an aqueous solution of a salt. Two electrodes, an anode 6 and a cathode 8, are wired to a current source, such as a battery 10. When the apparatus is electrified, metal atoms in the anode 6 are ionized by the electricity and go into the solution as ions. Depending on the chemistry of the metals and salt, the metal ions from anode 6 either plate the cathode 8, fall out as precipitate, or remain in solution.
When used for planarization of metal films on semiconductior wafers, conventional electrochemical planarization presents the disadvantage that the metal may not be selectively removed from the wafer. While existing electrochemical planarization techniques are known to “smooth” a metal layer, they are limited by topography dimensions and do not achieve true planarization. FIG. 2 shows a dielectric layer 12 having trenches, or vias, and having a barrier metal layer 20 thereon. A metal layer 14 is deposited on the wafer over the barrier layer, filling the trenches. After being deposited on barrier layer 20, metal layer 14 may not be completely flat but, rather, may have areas of high topography 16 and low topography 18. With conventional electrochemical planarization, when the areas of high topography and low topography are of large dimension, selectivity of etching is reduced and the metal layer is removed uniformly, so that the areas of high topography and low topography remain. In addition, chemical saturation may act to inhibit selective etching in areas of small dimension topography. At the start of a conventional electrochemical planarization process, metal ions dissociate from the metal layer and enter the electrolytic solution, saturating the electrolytic solution close to the metal layer. When current is applied, a rapid increase of metal ions into the solution creates an “anode film.” As the anode film becomes saturated with metal ions, the planarization process slows down or stops in response to the increase in the anode film metal ion saturation level. Thus, with conventional electrochemical planarization, uniform planarization is not achieved.
For uniform planarization, “step-height reduction” is desired, that is, the selective removal of the metal layer at the high topography areas, followed by uniform removal of the metal layer, both locally and globally. Step-height reduction should result in metal remaining only in the trenches and vias with a flat surface therein, as illustrated in FIG. 3.
Accordingly, there exists a need for an electrochemical planarization method and apparatus which accomplishes improved step-height reduction of metal layers on substrates, followed by uniform planarization of the metal layer.